1. Field of Invention
The present invention relates to a thin film transistor structure. More particularly, the present invention relates to an arrangement of a gate structure of a thin film transistor.
2. Description of Related Art
One of various techniques for fabricating thin film transistors is a lateral grain growth technique named heat retaining layer enhanced crystallization (HREC). FIG. 1 is a schematic cross-sectional view of the technique. As shown in FIG. 1, a strip-shaped amorphous silicon island pattern 102 is formed on a substrate 100, and a heat retaining layer (HRL) 104 is then formed thereon. Thereafter, the strip-shaped amorphous silicon island layer is subject to a laser annealing procedure, such that the strip-shaped amorphous silicon island layer is melted and induced to produce a super lateral grain grown crystalline silicon. The method takes the advantage of the characteristic that the HRL is capable of partially absorbing a particular laser spectrum. Thus, after a part of laser energy is absorbed by the HRL, a continuous supplementary heating effect is exerted on the amorphous silicon, thereby facilitating reducing the cooling speed of the melted silicon during laser crystallization. Accordingly, a longer lateral grain growth is achieved.
FIG. 2 is a top view of a thin film transistor (TFT) fabricated by the conventional definition. First, a silicon island 10 is formed by using the aforementioned manner. As shown in FIG. 2, the crystalline silicon island formed through laser annealing has a longitudinal primary grain boundary P in the middle, and secondary grain boundaries, also referred to as a lateral grain boundary, being substantially perpendicular to the longitudinal primary grain boundary P. During the fabrication of the transistor, the electric current is designed to flow in a direction parallel to the grain boundary in order to make the current flowing smoothly. Therefore, as shown in FIG. 2, a gate 20 is located over the longitudinal primary grain boundary P, while source/drain regions 24 are located at the left and right sides of the primary grain boundary P. In addition, a gate contact 22 is further electrically connected to the gate 20. With this structure, after the transistor is turned on, the current I flows in a direction parallel to the grain boundary, and is only blocked by the primary grain boundary P in the midway. As such, high carrier mobility and superior device quality can be obtained.
Although such a design can provide better device properties, the active region of the amorphous silicon must be patterned first in the technique of using the heat retaining layer enhanced crystallization (H-REC) to obtain the lateral grown polysilicon. The width W of the amorphous silicon island is limited to be greater than the channel length L due to the above step, such that the direction of the lateral grain growth is parallel to the direction of the current flow, and high carrier mobility and control of the grain position can be obtained. In other words, the conventional method of defining the channel length L by a gate region and defining the channel width W by the dimension of the active region limits the device dimension, i.e., the width is larger than the length. Therefore, the device dimension has only few variations in circuit design.
In summary, the TFT manufactured by the conventional technique described above is limited to that the width W thereof must be larger than the channel length L, which results in low design freedom of device dimensions. Furthermore, if the width of the channel region of component is intended to be smaller than the length, an additional mask and photolithography process must be added. Thus, the process cost is increased due to the expensive mask and the complex process procedures.
Accordingly, it has become an urgent matter, under the current grain growth method, how to enhance the design freedom of device dimension so as to increase the adaptability, and how to change the device dimension without adding additional masks so as to reduce the process cost.